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CXA3086Q
6-bit 140MSPS Flash A/D Converter
Description The CXA3086Q is an 6-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 140MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. Features * Differential linearity error: 0.2LSB or less * Integral linearity error: 0.2LSB or less * High-speed operation with a maximum conversion rate of 140MSPS * Low input capacitance: 7pF * Wide analog input bandwidth: 200MHz * Low power consumption: 358mW * Low error rate * Excellent temperature characteristics * 1: 2 demultiplexed output * 1/2 frequency divided clock output (with reset function) * Compatible with ECL, PECL and TTL digital input levels * Single +5V power supply operation available * Surface mounting package
P2D5 (MSB) RESETN/E RESET/E RESETN/T
48 pin QFP (Plastic)
Structure Bipolar silicon monolithic IC Applications * Magnetic recording (PRML) * Communications (QPSK, QAM) * LCDs * Digital oscilloscopes
P2D0 (LSB)
2
P2D4
P2D3
P2D2
12 11 10 DVEE3 13 AGND 14 VRBS 15 VRB 16 AVCC 17 N.C. 18 VIN 19 AVCC 20 VRT 21 VRTS 22 AGND 23 DGND3 24
9
8
7
6
5
P2D1
Pin Configuration (Top View)
DGND2
4
3
DGND2
1 48 DVCC2 47 DVCC1 46 DGND1 45 N.C. 44 PS 43 CLKOUT 42 INV 41 SELECT 40 N.C. 39 DGND1 38 DVCC1 37 DVCC2
25 26 27 28 29 30 31 32 33 34 35 36
DVCC2
P1D2
P1D4
CLKN/E
P1D0 (LSB)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
P1D5 (MSB)
DGND2
DGND2
DVCC2
CLK/E
CLK/T
P1D1
P1D3
E95619C77
CXA3086Q
Absolute Maximum Ratings (Ta = 25C) * Supply voltage AVCC, DVCC1, DVCC2 DGND3 DVEE3 DGND3 - DVEE3 -0.5 to +7.0 -0.5 to +7.0 -7.0 to +0.5 -0.5 to +7.0 Unit V V V V
VIN VRT - 2.7 to AVCC V VRT 2.7 to AVCC V VRB VIN - 2.7 to AVCC V |VRT - VRB| 2.5 V * Digital input voltage ECL (/E1) DVEE3 to +0.5 V PECL (/E) -0.5 to DGND3 V TTL (/T, INV, PS) -0.5 to DVCC1 V other (SELECT) -0.5 to DVCC1 V VID2 (|/E - N/E|) 2.7 V * Storage temperature Tstg -65 to +150 C * Allowable power dissipationPD 1.2 W (when mounted on a glass fabric base epoxy board with 76mm x 114mm, 1.6mm thick) Recommended Operating Conditions With a single power supply With dual power supplies Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V DGND1, DGND2, AGND -0.05 0 +0.05 -0.05 0 +0.05 V DGND3 +4.75 +5.0 +5.25 -0.05 0 +0.05 V -0.05 0 +0.05 -5.5 -5.0 -4.75 V DVEE3 Analog input voltage VIN VRB VRT VRB VRT V Reference input voltage VRT +2.9 +4.1 +2.9 +4.1 V VRB +1.4 +2.6 +1.4 +2.6 V |VRT - VRB| 1.5 2.1 1.5 2.1 V Digital input voltage ECL (/E) : VIH DGND3 - 1.05 DGND3 - 0.5 V : VIL DGND3 - 3.2 DGND3 - 1.4 V PECL (/E) : VIH DGND3 - 1.05 DGND3 - 0.5 V : VIL DGND3 - 3.2 DGND3 - 1.4 V TTL (/T, INV, PS): VIH 2.0 2.0 V : VIL 0.8 0.8 V other (SELECT) : VIH DVCC1 DVCC1 V : VIL DGND1 DGND1 V 2 (|/E - N/E|) VID 0.4 0.8 0.4 0.8 V Maximum conversion rate Fc (Straight mode) 100 100 MSPS (DMUX mode) 140 140 MSPS Ambient temperature Ta -20 +75 -20 +75 C
* Analog input voltage * Reference input voltage
*
* *
*
* *
1 /E and /T indicate CLK/E and CLK/T, etc. for the pin name. 2 VID: Input Voltage Differential ECL and PECL switching level
DGND3 VIH (max.) VIL VTH (DGND3 - 1.2V) VID VIH VIL (min.)
-2-
CXA3086Q
Block Diagram
AVCC 17 20 VRTS 22 r1 VRT 21 r
1
INV 42
DVCC1 38 47 9
DVCC2 28 37 48
DGND3 24
(MSB) 35 P1D5 34 P1D4
r
LATCHA
TTLOUT
2
33 P1D3 32 P1D2 31 P1D1 30 P1D0 (LSB)
r r VIN 19
* * *
30
6bit
31
6bit LATCH
ENCODER
r
32
6bit
6bit
r
33
(MSB) 7 P2D5 6 P2D4
LATCHB
6bit
TTLOUT
r r r2 VRB 16 VRBS 15 r
* * *
62
5 P2D3 4 P2D2 3 P2D1 2 P2D0 (LSB)
63
CLK/T 27 CLK/E 25 CLKN/E 26 D RESETN/T 10 RESETN/E 12 RESET/E 11 14 23 AGND 44 PS 41 SELECT 39 46 DGND1 1 8 29 36 DGND2 13 Q Q Select
Delay
18 40 45 N.C.
43 CLKOUT
DVEE3
-3-
CXA3086Q
Pin Description and I/O Pin Equivalent Circuit Pin No. 14, 23 Symbol AGND I/O Standard voltage level GND +5V (typ.) Equivalent circuit Description Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground.
17, 20
AVCC
1, 8, DGND1 29, 36, DGND2 39, 46 9, 28, DVCC1 37, 38, DVCC2 47, 48
GND
+5V (typ.) +5V (typ.) (With a single power supply) GND (With dual power supplies) GND (With a single power supply) -5V (typ.) (With dual power supplies)
Digital power supply.
24
DGND3
Digital power supply. Ground for ECL input. +5V for PECL and TTL input.
13
DVEE3
Digital power supply. -5V for ECL input. Ground for PECL and TTL input.
18, 40, N.C. 45 25 CLK/E I
No connected pin. Not connected with the internal circuits. Clock input. CLK/E complementary input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. -4-
DGND3
26
CLKN/E
I
r 12 25 r
ECL/ PECL 12 RESETN/E I
11 26
1.2V
r
r
DVEE3
11
RESET/E
I
CXA3086Q
Pin No.
Symbol
I/O
Standard voltage level
Equivalent circuit
DVCC1
Description
27
CLK/T
I
r/2
Clock input.
TTL
10 27 r
1.5V
10
RESETN/T
I
DGND1 DVEE3
Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) Power saving input. When the input is set to low level, the power saving mode is set. In this time the all TTL outputs go into the high-impedance state. Normally, set to high level or left open.
42
INV
I
DVCC1
TTL 44 PS I
42 44
DGND1 DVEE3
DVCC1
41
SELECT
Vcc or GND
41
Data output mode selection. (See Table 2. Operating Mode Table.)
DGND1 DVEE3
22
VRTS
O
+4.0V (typ.)
22 21 r1 r Comparator 1 r
Reference voltage sense. By-pass to AGND with a 0.1F chip capacitor. Top reference voltage. By-pass to AGND with a 1F tantal capacitor and a 0.1F chip capacitor. Bottom reference voltage. By-pass to AGND with a 1F tantal capacitor and a 0.1F chip capacitor. Reference voltage sense. By-pass to AGND with a 0.1F chip capacitor.
21
VRT
I
VRTS +r1 x Iref
r Comparator 2 r
16
VRB
I
VRBS -r2 x Iref
r Comparator 62 r r Comparator 63 r2 r
15
VRBS
O
+2.0V (typ.)
16 15
-5-
CXA3086Q
Pin No.
Symbol
I/O
Standard voltage level
AVCC
Equivalent circuit
Comparator AVCC
Description
19
VIN
I
VRT to VRB
Analog input.
19 Vref
DVEE3
AGND
30 to 35 2 to 7
P1D0 to P1D5 P2D0 to P2D5
O
DVCC1 DVCC2
Port 1 side data output.
O
TTL
100k
2
to
7
30 to 35 43 DGND2 DVEE3
Port 2 side data output.
DGND1
43
CLKOUT
O
Clock output. (See Table 2. Operating Mode Table.)
-6-
CXA3086Q
Electrical Characteristics (DVCC1, 2, AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25C) Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Residual resistance r1 r2 Digital input (ECL, PECL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance Digital input (TTL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance EIL EDL CIN RIN IIN Rref3 Iref4 r1 r2 VIH VIL VTH IIH IIL Symbol Conditions Min. Typ. 6 0.2 0.2 7 16 0 160 6.5 3.0 3.0
DGND3 - 1.05 DGND3 - 3.2 DGND3 - 1.2
Max.
Unit bits LSB LSB pF k A mA V V V A A pF V V V A A pF V V A MSPS ps ns ns ns ns ns ns ns ns ns ns
VIN = 2Vp-p, Fc = 5MSPS
VIN = +3.0V + 0.07Vrms
150 125 225 9.0 4.2 4.2 308 12.5 5.7 5.7
DGND3 - 0.5 DGND3 - 1.4
VIH = DGND3 - 0.8V VIL = DGND3 - 1.6V
-50 -75
+50 0 5
VIH VIL VTH IIH IIL
2.0 0.8 1.5 VIH = 3.5V VIL = 0.2V -50 -500 0 0 5
Digital output (TTL) Digital output voltage : High VOH : Low VOL Leak current during output off IOZ Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock low pulse width RESET Signal setup time RESET Signal hold time CLKOUT output delay Data output delay Output rise time Output fall time Fc Taj Tds Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2 Tr Tf
IOH = -2mA IOL = 1mA Power saving mode DMUX mode
2.4 -15 140 3 2.9 2.9 3.5 0 4.5 T5 6.5 10 4.5 6 0.5 70
CLK CLK RESETN - CLK RESETN - CLK DMUX mode 0.8 to 2.0V 0.8 to 2.0V (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF)
7 T+1 8 2 2
8 T+2 10
These characteristics are for PECL input, unless otherwise specified.
-7-
CXA3086Q
Item Dynamic characteristics Input bandwidth S/N ratio
Symbol
Conditions VIN = 2Vp-p, -3dB Fc = 140MSPS, fin = 1kHz Fs DMUX mode Fc = 140MSPS, fin = 34.999MHz Fs DMUX mode Fc = 140MSPS, fin = 1kHz Fs DMUX mode Error > 4LSB Fc = 140MSPS, fin = 34.999MHz Fs DMUX mode Error > 4LSB Fc = 100MSPS, fin = 24.999MHz Fs straight mode Error > 4LSB
Min. 200
Typ.
Max.
Unit MHz dB
{ {
37.0
34.5
dB TPS6
Error rate
{ { {
10-12
10-9
TPS
10-9
TSP
Power supply Supply current Supply current Power consumption Supply current Power consumption
ICC IEE Pd7 ICC + IEE Pd
Power saving mode Power saving mode
54.0 0.4 290 2.0 28
67.5 0.6 360
90 0.8 470 8.0 58
mA mA mW mA mW
3 Rref: Resistance value between VRT and VRB 4 Iref = VRT - VRB Rref 1 5 T = Fc 6 TPS: Times Per Sample 7 Pd = (ICC + IEE) * VCC + (VRT - VRB) 2 Rref INV VIN Step D5 VRTS 63 62 : 32 31 : 1 0 11111 11111 : 10000 01111 : 00000 00000 1 D0 D5 10000 00000 : 00111 11000 : 11111 01111 0 D0 00 01 11 00 10 11
VRBS
Table 1. I/O Correspondence Table
63 62 61 60 59 58 * * * * * * * 5 4 3 2 1 0
Step
1LSB
r1 x Iref
r2 x Iref
VRT VRTS VIN
VRBS VRB
-8-
CXA3086Q
Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit
5V 5V 100MHz
Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit
A Icc
4V VRT AVCC DVCC1 DVCC2
A IEE
DGND3 OSC1 : Variable
Amp
VIN fr CLK/E 5MHz PECL CLK OSC2 DVEE3 100MHz ECL Buffer CXA3086Q
6
1.95V
VIN
Logic Analizer 1024 samples
2V
VRB
DGND2 DGND1 AGND
Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit
+V
Aperture Jitter Measurement Method
VRT VIN
S2 S1: ON when A < B S2: ON when A > B CLK t AB Comparator VIN CXA3086Q 6 A6 to A1 A0 "0" DVM Controller B6 to B1 B0 "1" 00***0 to 11***0 6 Buffer CLK VIN 33 32 31 30 29
VRB
S1
-V
(LSB)
Sampling timing fluctuation (= aperture jitter)
Where (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Taj is: Taj = / t = / ( 64 2 x 2f )
Error Rate Measurement Circuit
VIN 6 A B CLK CLK + Latch
Signal Source
CXA3086Q
Latch
Comparator A>B
Pulse Counter
FC - 1kHz 4 2Vp-p Sin Wave
4LSB Signal Source FC 1/8
-9-
CXA3086Q
Description of Operating Modes The CXA3086Q has two types of operating modes which are selected with Pin 41 (SELECT). Operating mode DMUX mode Straight mode SELECT VCC GND Maximum conversion rate 140MSPS 100MSPS Data output Demultiplexed output 70Mbps Straight output 100Mbps Clock output The input clock is 1/2 frequency divided and output. 70MHz The input clock is inverted and output. 100MHz
Table 2. Operating Mode Table
1. DMUX mode (See Application Circuits (1), (2) and (3).) Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the RESETN pin (Pin 10 or 12). The RESET signal requires the setup time (T_rs 3.5ns) and hold time (T_rh 0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge. The reset period can be extended by making the low level period of the RESET signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is regarded as not important, the timing where the RESET signal is set from high to low is not so consequence. However, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary. See the timing chart for detail. (This chart shows the example of reset for 2T.) The A/D converter can operate at FC (min.) = 140MSPS in this mode.
- 10 -
CXA3086Q
When the RESET signal is not used.
CLK
CXA3086Q CLK
CLK
CLKOUT 6bit DATA
AA
RESETN
CXA3086Q
CLK
CLKOUT 6bit DATA
BB
RESETN
When the RESET signal is used.
CLK RESET signal CXA3086Q CLK
CLK RESETN
CLKOUT 6bit DATA
(Reset period)
A
CXA3086Q
CLK
CLKOUT 6bit DATA
(Reset period)
B
RESET signal
RESETN
2. Straight mode (See Application Circuits (4), (5) and (6).) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings The logic input level for the CXA3086Q supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. Digital input level ECL PECL TTL DVEE3 -5V 0V 0V DGND3 0V +5V +5V Supply voltage Application circuits 5V +5V +5V (1) (4) (2) (5) (3) (6)
Table 3. Logic Input Level and Power Supply Settings - 11 -
CXA3086Q
Application Circuit 1 (1) DMUX ECL input
+5V (D) DG ECL RESET Signal 12 11 10 9 -5V (D) AG 2V AG +5V (A) AG +5V (A) AG AG DG 4V 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ECL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data Latch 6 bit Digital Data 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D) DG P2D0 to P2D5 6 bit Digital Data Latch 6 bit Digital Data
(2) DMUX PECL input
+5V (D) DG PECL RESET Signal 12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PECL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data 6 bit Digital Data Latch 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D) DG P2D0 to P2D5 6 bit Digital Data Latch 6 bit Digital Data
(3) DMUX TTL input
+5V (D) DG TTL RESET Signal 12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TTL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data 6 bit Digital Data Latch 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D) 6 bit Digital Data Latch
DG
P2D0 to P2D5 6 bit Digital Data
- 12 -
CXA3086Q
(4) Straight ECL input
+5V (D) DG DG
12 11 10 9 -5V (D) AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG DG 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 ECL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data Latch 6 bit Digital Data
ECL
TTL
(5) Straight PECL input
+5V (D) DG DG
12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 PECL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data Latch 6 bit Digital Data
PECL
TTL
(6) Straight TTL input
+5V (D) DG DG
12 11 10 9 DG AG 2V AG +5V (A) AG +5V (A) AG AG +5V (D) 4V 13 14 15 16 17 18 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 TTL-CLK DG +5V (D) DG P1D0 to P1D5 6 bit Digital Data Latch 6 bit Digital Data
- 13 -
CXA3086Q
Application Circuit 2
AG
Straight Mode TTL I/O (When a single power supply is used)
1F 4V
Analog input AG AG
+5V (A)
AG AG 1F
VRTS short
10F
2V VRBS short
DG
24
23
22
21
20
19
18
17
16
15
14
13
VIN
DGND3
N.C.
AGND
AVCC
VRTS
VRB
VRBS
VRT
AGND
AVCC
25 CLK/E TTL CLK 26 CLKN/E 27 CLK/T 28 DVCC2 29 DGND2 (LSB) P1D0 P1D1 P1D2 P1D3 P1D4 (MSB) P1D5 30 P1D0 31 P1D1 32 P1D2 33 P1D3 34 P1D4 35 P1D5
RESETN/E 12 RESET/E 11 RESETN/T 10 DVCC2 9 DGND2 8 P2D5 7 P2D4 6 P2D3 5 P2D2 4 P2D1 3 P2D0 2 P2D5 (MSB) P2D4 P2D3 P2D2 P2D1 P2D0 (LSB)
CLKOUT
SELECT
DGND1
DGND1
36 DGND2
DVCC2
DVCC1
DVCC1
47
INV
37
38
39
40
41
42
43
44
45
46
48
10F
DG +5V (D)
Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1F.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 14 -
CLKOUT
DVCC2
N.C.
N.C.
PS
DVEE3
DGND2 1
CXA3086Q
DMUX Mode Timing Chart (Select = VCC)
Tds N-1 VIN N+3 N T N+1 CLK Tpw1 Tpw0 Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) P1D0 to D5 N+1 2.0V 0.8V 2.0V 0.8V T N+2 N+4 4.5ns (typ.) N+5
N+6 N+7
N+3
P2D0 to D5 Td_clk; 7ns (typ.) 8ns (max.) 4.5ns (min.) CLK OUT 2.0V (Reset period) 0.8V 4.5ns (min.) 8ns (max.) T_rh T_rs T_rh T_rs Td_clk 2.0V 0.8V
N
N+2 T
Tdo1 T + 1ns (typ.) 2.0V 0.8V
RESET signal
- 15 -
CXA3086Q
Straight Mode Timing Chart (Select = GND)
N-1 VIN Tds 4.5ns (typ.) T N N+1
N+2
N+3
CLK Tpw1 Tpw0
Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V 0.8V
P1D0 to D5
N-4
N-3
N-2
N-1
N
P2D0 to D5
N-5
2.0V 0.8V
N-4
N-3
N-2
N-1
Td_clk; 7ns (typ.) 4.5ns (min.) 8ns (max.)
CLK OUT (CLK is inverted and output.)
2.0V 0.8V
RESET signal
- 16 -
CXA3086Q
Timing of A/D Converter and Peripheral Circuit In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is described in detail as below. For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data delay are showed in the following specification, i.e. Td_clk 4.5ns (min.) to 8.0ns (max.) Tdo2 6.5ns (min.) to 10ns (max.) These values are considered in all the temperature change and power supply variation. When the maximum clock rate 140MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the 3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be changed in same trend at the same condition of the temperature change and power supply variation. As a result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also, 0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay can be omitted in this case. When Ta = 25C, VCC = +5V, the clock delay and data delay are Td_clk 5.0ns (min.) to 7.5ns (max.) Tdo2 7.0ns (min.) to 9.5ns (max.) The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the set-up time for the data latching can be obtained as ts (min.) = 2.5ns. The output delay change of the DATA OUT and CLK OUT due to the temperature change and the power supply variation should have the same trend of the delay change, the minimum ts = 2.5ns can be guaranteed at any temperature change and power supply variation.
Analog input R CXA3086Q Vin P1D/out CLK P2D/out RESET CLK OUT CXA3086Q Vin P1D/out CLK P2D/out RESET CLK OUT CXA3086Q Vin P1D/out CLK P2D/out RESET CLK OUT 7ns ( = 1/140MSPS) 6bit 6bit Gate Array Latch
Analog input G
6bit 6bit
Analog input B CLK RESET
6bit 6bit
CLK th-reset RESET signal
Td_clk (min.) 5.0ns <4.5ns> Td_clk (max.) 7.5ns <8.0ns> Tdo2 (min.) 7.0ns <6.5ns> Tdo2 (min.) 9.5ns <10ns> ts (min.) 2.5ns th (min.) 6.5ns
CLK OUT
P1D/out P2D/out
14ns
Note: In the timing chart, the values in the brackets < > are included all the temperature change and the power supply variation. - 17 -
CXA3086Q
Notes on Operation * The CXA3086Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. * The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. -- The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. -- To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. -- Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a 0.1F or larger ceramic chip capacitor. (Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.) -- The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. * The analog input pin VIN has an input capacitance of approximately 7pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. * The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them to AGND with an approximately 1F tantal capacitor and 0.1F chip capacitor as short as possible. * The offset for residual resistance is generated each for the reference voltage pins VRT and VRB. When the offset voltage has no influence on the IC operation, the voltage should be applied to the VRT and VRB pins directly, keeping the VRBS pin open. When the reference voltage is to be supplied to these pins precisely, form the feedback loop circuit with VRT and VRB as a force pin and adjust the offset voltage to be 0V. See the "Application Circuit 2" for details. * If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1F capacitor. At this time, approximately DGND3 - 1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. * When the digital input level is ECL or PECL level, /E pins should be used and /T pins left open. When the digital input level is TTL, /T pins should be used and /E pins left open.
- 18 -
CXA3086Q
Example of Representative Characteristics
Current consumption vs. Ambient temperature characteristics
70 90
Current consumption vs. Conversion rate characteristics
Current consumption [mA]
65
Current consumption [mA]
80
60
70
fin = fCLK - 1kHz 4 DMUX mode CL = 5pF
55
60
50 -25 25 Ta - Ambient temperature [C] 75
50 0 70 Fc - Conversion rate [MSPS] 140
Analog input current vs. Analog input voltage characteristics
11 100
Reference current vs. Ambient temperature characteristics
Analog input current [A]
Reference current [mA]
4
10
VRT = 4V VRB = 2V
9
50
8
7 0 2 3 Analog input voltage [V] -25 25 Ta - Ambient temperature [C] 75
- 19 -
CXA3086Q
SNR vs. Input frequency response
40
Error rate vs. Conversion rate characteristics
10-6
Fc = 140MSPS 10-7 35
Error rate [TPS]
fin = fCLK - 1kHz 4 Error > 4LSB
SNR [dB]
10-8
10-9
30 1 3 5 10 30 Input frequency [MHz] 50 100
10-10 140 160 180 Fc - Conversion rate [MSPS] 200
Maximum conversion rate vs. Ambient temperature characteristics
Fc - Maximum conversion rate [MSPS]
180 fCLK - 1kHz 4 Error > 4LSB Error rate: 10-9TPS fin =
170
160
150
140 -25 25 Ta - Ambient temperature [C] 75
- 20 -
CXA3086Q
CXA3086Q Evaluation Board Description The CXA3086Q Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3086Q. After latching the CXA3086Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector. Features * Resolution: * Maximum conversion rate: * Supply voltage: * Dual analog input pins:
6 bits 140MSPS (min.) 5.0V DIR.IN: AC coupling input pin AMP.IN: Operational amplifier input pin * Clock frequency division: 1/1 to 1/16 Absolute Maximum Ratings * Supply voltage VCC VEE
-0.5 to +7.0 -7.0 to +0.5
V V Min. +4.75 -5.25 -0.75 1.5 0.8 Typ. +5.0 0 -5.0 0 2.0 1.0 Max. +5.25 -4.75 +1.05 2.2 1.2
Recommended Operating Conditions * Supply voltage VCC GND VEE * Analog input AMP. IN DIR. IN * Clock input CLK. IN
V V V V Vp-p Vp-p
- 21 -
Block Diagram
VRB. R1
VRT. R2
OFFSET. R3
A/D D/A INV INV SELECT PS DMUX NORM NORM NORM Straight INV SW4 D/A OUT (-1.0V)
FULL SCALE. R4 FULL SCALE. R5
Vrb
Vrt
OFFSET
SW1
INV SW2 PS SW3
D/A OUT (-1.0V)
CON2
DIR IN 6 Vrt P2D0 to D5 A VIN CXA3086Q Vrb VRB CLK (PECL) (TTL) CLKOUT 6 6 (TTL) B S1 P1D0 to D5 VRT (TTL) (TTL) (ECL) 6 6
LATCH
AGND
270
TTL/ECL
AGND
DAC
51
CON4 P2 side OUT AGND
CON1
130
AMP IN
82
AGND
x (-2)
LATCH
CON3
CLK IN
VBB
TTL/ECL
1k
390
(ECL)
DAC
Counter
PECL/TTL
VEE
GND
VCC CON8 P1 side DATA CON7 P2 side DATA
CON6
TTL/ECL
- 22 -
4 (PECL) (TTL) S2 4 (TTL)
AGND
AGND
6
CON5 P1 side OUT AGND
51
0.1F
DGND
DGND
1k
(ECL)
CXA3086Q
CXA3086Q
Pin Description and I/O Level Pin No. CON1 CON2 Symbol AMP. IN DIR. IN I/O I I Standard I/O level 0.95Vp-p 2.0Vp-p Current Description Doubles the analog input signal amplitude using the operational amplifier. The input impedance is 50. AC coupling input. Suitable for sine waves and other repeating waveforms. The input impedance is 50. The CXA3086Q operates at the PECL level clock using the sine wave-to-PECL conversion circuit. The input impedance is 50. Allows the D/A converted waveform of the CXA3086Q port 2 side data to be observed. The output impedance is 50. Allows the D/A converted waveform of the CXA3086Q port 1 side data to be observed. The output impedance is 50. 0.8A The inside of the board is divided into analog and digital systems. -0.6A The CXA3086Q port 2 side data output is latched at the frequency divided clock and then output. The CXA3086Q port 1 side data output is latched at the frequency divided clock and then output.
CON3
CLK. IN
I
1.0Vp-p
CON4
P2 side OUT
O
0 to -1V
CON5
P1 side OUT VCC
O I I I O O
0 to -1V +5.0V 0V -5.0V TTL TTL
CON6
GND VEE
CON7 CON8
P2 side DATA P1 side DATA
Board Adjustments and Settings 1. VRB.R1: CXA3086Q VRB voltage adjusting volume. 2. 3. 4. 5. 6. VRT.R2: OFFSET.R3: FULL SCALE.R4: FULL SCALE.R5: S1: CXA3086Q VRT voltage adjusting volume. Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the CXA3086Q input range. Full-scale adjusting volume for the port 2 D/A output. (-1V: Typ.) Full-scale adjusting volume for the port 1 D/A output. (-1V: Typ.) Switching junction for the dual analog input pins. Set as follows according to the input pins used. Junction Symbol AMP.IN DIR.IN 7. S2: A OPEN 0.1F B SHORT 10k
8. 9. 10. 11.
SW1 SELECT: SW2 A/D INV: SW3 PS: SW4 D/A INV:
Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3086Q clock output. CXA3086Q output mode selector switch. CXA3086Q output polarity inversion switch. CXA3086Q PS switch. D/A converter output polarity inversion switch. - 23 -
CXA3086Q
Notes on Board Operation 1. The factory settings for the CXA3086Q Evaluation Board are as follows. VRB.R1 = 1.5V VRT.R2 = 3.0V OFFSET.R3 = 2.25V FULL SCALE.R4 = -1V FULL SCALE.R5 = -1V S1 S2 A : OPEN, B : SHORT 8 : SHORT (1/8 frequency division)
When using the board in this condition, the input signals should be input at the amplitudes shown below. (The frequency is set as desired.) Analog input signal: CON1 (AMP.IN)
0V center, 800mVp-p or less
Clock input signal: CON3 (CLK.IN)
0V center, 1.0Vp-p
2.
When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range of the A/D converter's analog input signal. When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited, but the VRT level may be limited by IC3: NJM3403A. In the evaluation board of the CXA3086Q, CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case.
3.
4.
- 24 -
CXA3086Q
CXA3086Q Evaluation Board Timing Chart
N N+1 CON2 DIR IN 2Vp-p 0V
N+3
N+2
CON3 CLK IN
1Vp-p
0V
CXA3086Q CLK
(PECL)
CXA3086Q P1 side DATA
N-4 (TTL) Approximately 6.0ns
N-3
N-2
N-1
CON8 P1 side DATA CLK
(TTL)
Approximately 9.0ns
CON8 P1 side DATA DATA
N-6 (TTL)
N-4
N-2
N-6 CON5 P1 side OUT (Analog regeneration waveform) 0 to -1V N-4 N-2
Operating Conditions
CXA3086Q operating mode : Straight mode Analog input : DIR IN pin input S2 setting : 1/2 frequency divided clock
- 25 -
CXA3086Q
Circuit Diagram
CON6 VEE GND VCC
L1 C1 33F
L2 C2 33F
L3
L4 C3 33F
L5
L6 DGND C4 33F SW4 D/A INV PS SW3 PS SW2 A/D INV DVCC SW1 SELECT DAINV
AVEE
DVEE
AGND
DGND
AVCC
DVCC
ADINV
SELECT
C24 0.1F DVCC AGND AVEE AGND AVEE DGND P2D5 P2D4 P2D3 P2D2 P2D1 AGND DGND R7 510 R1 2k D1 TL431CP R8 510 R2 1k R6 51 AVCC CON1 AMP IN R13 82 AGND AGND R14 130 AGND IC3C NJM3403A 10 8 9 C7 1F AGND C16 0.1F AVCC C8 1F AGND C17 0.1F AVCC DVCC AGND 2 3 R16 4 270 6 IC2 7 CLC404 R17 43 S1 AVCC C10 1F C21 0.1F C20 0.1F R3 10k R10 22k 12 11 10 RESETN/E RESETN/T R9 7.5k 2 3 11 1 4 IC3A NJM3403A R12 390k R11 200k AGND DGND IC3B NJM3403A 6 7 5 AGND CON2 DIR IN AGND R18 51 A B RESET/E 9 DVCC2 8 DGND2 7 P2D5 6 P2D4 5 P2D3 4 P2D2 3 P2D1 2 P2D0 1 DGND2 P2D0
C5 1F
C14 0.1F
C6 1F
C15 0.1F
AGND 13 DVEE3 14 AGND C9 1F AVCC C18 0.1F C19 0.1F 15 VRBS 16 VRB 17 AVCC 18 N.C. 19 VIN 20 AVCC 21 VRT 22 VRTS 23 AGND 24 DGND3 C27 0.1F
DVCC2 48 DVCC1 47 DGND1 46
DGND C28 0.1F
DVCC
C25 N.C. 45 0.1F PS 44
DGND PS CLKOUT ADINV SELECT
R15 270
IC1 CXA3086Q
CLKOUT 43 INV 42 SELECT 41 N.C. 40 C26 0.1F
DGND1 39
DGND
DVCC1 38 DVCC2 37 CLKN/E DGND2 DGND2 C27 0.1F DGND DVCC
P1D0
P1D1
25 26 27 28 29 30 31 32 33 34 35 36 DGND DVCC P1D5 P1D4 P1D3 P1D2 IC4B 10H116 (PECL) 7 10 9 6 IC4A 10H116 (PECL) 3 5 4 2 IC4C 10H116 (PECL) 15 13 12 14
P1D2
P1D3
P1D4
P1D5
DGND
CLK/T
DVCC2
CLK/E
CON3 CLK IN DGND
C13 0.1F R19 51 DGND
R23 82
DVCC
P1D1 P1D0 DGND C23 0.1F
R20 1k 11
R21 390
R22 1k
R24 130
13 CLK DGND 9 S1 7 S2 R25 130 R26 130 R27 130 DGND R28 82 R29 82 R30 82 DVCC 12 D0 11 D1 6 D2 5 D3 IC5 10H136 (PECL)
Cout 4
IC4D 10H116 (PECL)
Q3 3 Q2 2 Q1 15 Q0 14
1/16 1/8 1/4 1/2
CLK CLKN
- 26 -
CXA3086Q
DGND DVcc 1 C42 0.1F 2
IC15 74ALS541 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 IC14 74ALS541 9 11 DVCC DGND 1 OC 11 CLK 19 E Q5 14 NQ5 13 Q4 12 NQ4 11 2 1D 3 2D P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D IC6 74AS574 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 15 5D 16 4D 17 3D 21 0D 22 1D 23 2D IC9 100324 Q3 9 DVEE 1 MSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 DVEE C44 0.1F R48 620 R37 82 10 LSB 11 NC 12 NC 13 CLKN 14 CLK DVCC Q5 14 19 E DGND 1 OC 11 CLK P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 IC10 100324 NQ5 13 Q4 12 NQ4 11 Q3 9 DVEE DGND C45 0.1F R38 82 R49 620 IC12 CX20201-1 AGND 28 VREF 27 AVEE 26 NC 25 NC 24 C52 NC 23 0.1F NC 22 NC 21 OUT 20 NC 19 AGND 18 DGND 17 INV 16 DVEE 15 C53 0.1F DVEE AGND DGND R4 2k D2 TL431CP C11 1F AVEE C51 0.1F R42 1k R43 270 3 4 5 6 7 8 17 16 15 14 13 12 25 DGND 26 DGND C47 0.1F CON7 P2 side DATA
R47 620
AGND
NQ3 10 Q0 24 NQ0 Q1 NQ1 Q2 NQ2 1 2 3 5 4
AGND CON4 P2 side OUT
R39 130 R40 130 DVEE 1 MSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 IC13 CX20201-1 AGND 28 VREF 27 AVEE 26 NC 25 NC 24 NC 23 NC 22 NC 21 OUT 20 NC 19 AGND 18 DGND 17 INV 16 DVEE 15 C56 0.1F DVEE AGND DGND AGND CON5 P1 side OUT R5 2k C55 0.1F D3 TL431CP C12 1F AVEE C54 0.1F AGND
NQ3 10 Q0 24 NQ0 Q1 NQ1 Q2 NQ2 1 2 3 5 4
R44 1k
R45 270
2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D IC7 74AS574
1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12
15 5D 16 4D 17 3D 21 0D 22 1D 23 2D
DVEE DAINV CLKOUT C46 0.1F DGND DGND R51 620 DGND 1/16 19 OE 17 VBB CLKOUT 24 D0 1 D0N 23 D1 22 D1N 1/8 21 D2 20 D2N 1/4 16 D3 15 D3N 1/2 14 D4 13 D4N CLK CLKN DVCC R31 82 R32 82 C31 0.1F R33 82 R34 130 R35 130 R36 130 DGND P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 IC14 74ALS541 3 4 5 6 7 8 17 16 15 14 13 12 25 26 DGND CON8 P1 side DATA 12 D5 11 D5N Q5 10 S2 C43 0.1F Q4 9 1/1 DVCC 1 2 IC8 100390 Q2 4 1/4 Q3 8 1/2 11 A4 10 A3 Q1 3 1/8 7 A2 Q0 2 1/16 5 A1 IC11 10H124 6B Y1 2 R50 620
10 LSB 11 NC 12 NC 13 CLKN 14 CLK
Y1 4 Y2 1 Y2 3 R46 620 DVEE
Y3 15 Y3 12 Y4 14 Y4 13
C50 0.1F DGND R41 620 DVEE
DGND
- 27 -
CXA3086Q
Component List
No. Product name IC1 CXA3086Q IC2 CLC404AJE IC3 NJM3403AM IC4 MC10H116L IC5 MC10H136L IC6, 7 74AS574N IC8 100390 IC9, 10 100324PC IC11 MC10H124L IC12, 13 CXA20201A-1 IC14, 15 74ALS541N D1 to 3 TL431CP SW1 to 4 ATE1D-2F3-10 S1, 2 JX-1 CON1 to 5 01K0315 CON6 TJ-563 CON7, 8 (FAP-2601-1202) L1 to 6 ZBF503D-00 C1 to 4 Tantal capacitor C5 to 12 Tantal capacitor C13 Ceramic capacitor All parts other than those listed above Chip capacitor Function 6-bit A/D converter OP-AMP OP-AMP ECL Buffer ECL Countor TTL Latch PECLTTL conversion TTLECL conversion TTLECL conversion 10-bit D/A converter TTL Buffer Shunt regulator Toggle switch Short pin BNC connector Power supply connector Flat cable connector Ferrite-bead filter 33F 1F 0.1F 0.1F No. R2 R1, 4, 5 R3 R47 to 51 R6, 18, 19 R7.8 R9 R10 R11 R12 R13, 23, 28 to 33, 37, 38 R14, 24 to 27, 34 to 36, 39, 40 R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41, 46 Product name RJ-5W-1K RJ-5W-2K RJ-5W-10K RGLD4X621J FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) Function 1k volume resistor 2k volume resistor 10k volume resistor 620 network resistor 51 510 7.5k 22k 200k 390k 82 130 270 43 1k 390 620
CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.)
Component side silk diagram - 28 -
CXA3086Q
Component side pattern diagram
Solder side pattern diagram
- 29 -
CXA3086Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05
36
25
0.15
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.12 M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 30 -
0.9 0.2
13.5

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